cells · geometry · flashHwFunc — Maximum Flexibility

General Model

flowchart LR
  CFG[fs_config.json] --> CELLS[cells]
  CFG --> GEO[geometry]
  CFG --> HW[flashHwFunc]
  CELLS --> MAC1["FLASHLINK_CELL macros"]
  GEO --> MAC2[BASE/REGION/ERASE]
  HW --> MAC3["STORAGE_DRV_FUNC + driver"]
  MAC1 --> INIT[FS_HARDWARE_INIT]
  MAC2 --> INIT
  MAC3 --> INIT

cells

Logical storage slicing. For FlashLink: cell size, file name field, and data capacity.

"cells": {
  "cellSize": 1024,
  "nameSize": 64,
  "cellDataSize": 956,
  "cellCount": 10
}

→ FLASHLINK_CELL_SIZE, FLASHLINK_NAME_SIZE, FLASHLINK_CELL_DATA_SIZE, FLASHLINK_CELL_COUNT

geometry

Physical memory region. Base address, total size, erase/program units.

"geometry": {
  "baseAddr": "0x080A0000",
  "regionSize": 131072,
  "eraseBlockSize": 4096
}

→ FLASHLINK_BASE_ADDR, FLASHLINK_REGION_SIZE, FLASHLINK_ERASE_BLOCK_SIZE

flashHwFunc

Hardware callback injection. read/prog/erase/sync function names and driver header path.

"flashHwFunc": {
  "drvSrcPath": "Driver/.../McuInternalFlashDrv_Stm32f407.h",
  "readFunc": "internalStm32f407FlashRead",
  "writeFunc": "internalStm32f407FlashProg",
  "eraseFunc": "internalStm32f407FlashErase",
  "syncFunc": "internalStm32f407FlashSync"
}

→ STORAGE_DRV_FUNC_READ, *_PROG, *_ERASE, *_SYNC

Same Code, Different Hardware

flowchart TD
  subgraph SameCode["Same FlashLink Code"]
    FS[fs_port_flashLink.c]
  end

  subgraph HW1["STM32F407 Internal Flash"]
    D1[McuInternalFlashDrv_Stm32f407]
  end

  subgraph HW2["W25Q128 External SPI"]
    D2[Ext_spi_flash_W25Qxx_driver]
  end

  JSON[fs_config.json] -->|flashHwFunc A| D1
  JSON -->|flashHwFunc B| D2
  FS --> D1
  FS --> D2

Only drvSrcPath and function names in JSON change. FS code stays the same.